In contemporary digital circuit applications, it is common to combine various logic structures using, for example, ECL, CMOS and TTL design. While CMOS and TTL are generally compatible, ECL uses substantially different voltages to represent a logical high and a logical low. In conventional ECL, -1.7 volts is used to represent a logical low and -0.95 volts is used to represent a logical high. Pseudo-ECL logic may also be used in order to take advantage of existing voltage supply rails. For example, with 0 volt and 5 volt supply rails, a pseudo-ECL circuit would use a signal of 3.3 volts for a logical low and a signal of 4.05 volts for logical high.
Because different voltages are often used in a single circuit, it is necessary to provide circuitry for translating ECL signals to suitable CMOS or TTL counterparts. Various circuits have been designed to translate the ECL signals to CMOS-compatible or TTL-compatible signals. An ECL signal, however, must propagate through the translator to the inputs of the CMOS or TTL circuits. Consequently, the propagation delay time through the translator becomes very important.
Translation propagation times of 1-2 nanoseconds are considered short for modern technology. Nonetheless, a propagation delay of this magnitude may be unacceptable for many applications.
Therefore, a need has arisen for a circuit and method for providing ECL-to-CMOS/TTL translations such that the propagation delay associated with both low-to-high transitions and high-to-low transitions is minimized.